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<div class="title">xwdttb_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gab5ddc5730a86f3cbab203b333b01595e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gab5ddc5730a86f3cbab203b333b01595e">XWDTTB_HW_H_</a></td></tr>
<tr class="memdesc:gab5ddc5730a86f3cbab203b333b01595e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="group__wdttb__v4__0.html#gab5ddc5730a86f3cbab203b333b01595e">More...</a><br /></td></tr>
<tr class="separator:gab5ddc5730a86f3cbab203b333b01595e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register offsets for the AXI Timebase WDT core. Each register is 32</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>bits. </p>
</div></td></tr>
<tr class="memitem:ga7acdd92b397bdfb0e14b649d4525bb2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga7acdd92b397bdfb0e14b649d4525bb2b">XWT_TWCSR0_OFFSET</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:ga7acdd92b397bdfb0e14b649d4525bb2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control/Status Register 0 Offset.  <a href="group__wdttb__v4__0.html#ga7acdd92b397bdfb0e14b649d4525bb2b">More...</a><br /></td></tr>
<tr class="separator:ga7acdd92b397bdfb0e14b649d4525bb2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5342d8af54e416c23b56a3dd9904e62b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga5342d8af54e416c23b56a3dd9904e62b">XWT_TWCSR1_OFFSET</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga5342d8af54e416c23b56a3dd9904e62b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control/Status Register 1 Offset.  <a href="group__wdttb__v4__0.html#ga5342d8af54e416c23b56a3dd9904e62b">More...</a><br /></td></tr>
<tr class="separator:ga5342d8af54e416c23b56a3dd9904e62b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd80f8a65e758f3862b655495b41561a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gacd80f8a65e758f3862b655495b41561a">XWT_TBR_OFFSET</a>&#160;&#160;&#160;0x08U</td></tr>
<tr class="memdesc:gacd80f8a65e758f3862b655495b41561a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timebase Register Offset.  <a href="group__wdttb__v4__0.html#gacd80f8a65e758f3862b655495b41561a">More...</a><br /></td></tr>
<tr class="separator:gacd80f8a65e758f3862b655495b41561a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register offsets for the AXI Timebase WDT core with windowing</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>feature with basic mode.</p>
<p>Each register is 32 bits. </p>
</div></td></tr>
<tr class="memitem:ga5179e62af141b56b29af9e69cbbb8591"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga5179e62af141b56b29af9e69cbbb8591">XWT_MWR_OFFSET</a>&#160;&#160;&#160;0x0CU</td></tr>
<tr class="memdesc:ga5179e62af141b56b29af9e69cbbb8591"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Write Control Register Offset.  <a href="group__wdttb__v4__0.html#ga5179e62af141b56b29af9e69cbbb8591">More...</a><br /></td></tr>
<tr class="separator:ga5179e62af141b56b29af9e69cbbb8591"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3479cb274c0cfc1e467737608d3de88b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga3479cb274c0cfc1e467737608d3de88b">XWT_ESR_OFFSET</a>&#160;&#160;&#160;0x10U</td></tr>
<tr class="memdesc:ga3479cb274c0cfc1e467737608d3de88b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable &amp; Status Register Offset.  <a href="group__wdttb__v4__0.html#ga3479cb274c0cfc1e467737608d3de88b">More...</a><br /></td></tr>
<tr class="separator:ga3479cb274c0cfc1e467737608d3de88b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7bb4b18a3b560ebc5b08216880f84e71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga7bb4b18a3b560ebc5b08216880f84e71">XWT_FCR_OFFSET</a>&#160;&#160;&#160;0x14U</td></tr>
<tr class="memdesc:ga7bb4b18a3b560ebc5b08216880f84e71"><td class="mdescLeft">&#160;</td><td class="mdescRight">Function Control Register Offset.  <a href="group__wdttb__v4__0.html#ga7bb4b18a3b560ebc5b08216880f84e71">More...</a><br /></td></tr>
<tr class="separator:ga7bb4b18a3b560ebc5b08216880f84e71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga82d67efeaf5c58cebc1966fd96e4fac0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga82d67efeaf5c58cebc1966fd96e4fac0">XWT_FWR_OFFSET</a>&#160;&#160;&#160;0x18U</td></tr>
<tr class="memdesc:ga82d67efeaf5c58cebc1966fd96e4fac0"><td class="mdescLeft">&#160;</td><td class="mdescRight">First Window Configuration Register Offset.  <a href="group__wdttb__v4__0.html#ga82d67efeaf5c58cebc1966fd96e4fac0">More...</a><br /></td></tr>
<tr class="separator:ga82d67efeaf5c58cebc1966fd96e4fac0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab663dabd33fca2fd450305fd3e325f63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gab663dabd33fca2fd450305fd3e325f63">XWT_SWR_OFFSET</a>&#160;&#160;&#160;0x1CU</td></tr>
<tr class="memdesc:gab663dabd33fca2fd450305fd3e325f63"><td class="mdescLeft">&#160;</td><td class="mdescRight">Second Window Configuration Register Offset.  <a href="group__wdttb__v4__0.html#gab663dabd33fca2fd450305fd3e325f63">More...</a><br /></td></tr>
<tr class="separator:gab663dabd33fca2fd450305fd3e325f63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5eda163c25dfcd74c15bf08ed8c1328e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga5eda163c25dfcd74c15bf08ed8c1328e">XWT_TSR0_OFFSET</a>&#160;&#160;&#160;0x20U</td></tr>
<tr class="memdesc:ga5eda163c25dfcd74c15bf08ed8c1328e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Task Signature Register 0 Offset.  <a href="group__wdttb__v4__0.html#ga5eda163c25dfcd74c15bf08ed8c1328e">More...</a><br /></td></tr>
<tr class="separator:ga5eda163c25dfcd74c15bf08ed8c1328e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e231a73df7e205e266fb1198e222814"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga1e231a73df7e205e266fb1198e222814">XWT_TSR1_OFFSET</a>&#160;&#160;&#160;0x24U</td></tr>
<tr class="memdesc:ga1e231a73df7e205e266fb1198e222814"><td class="mdescLeft">&#160;</td><td class="mdescRight">Task Signature Register 1 Offset.  <a href="group__wdttb__v4__0.html#ga1e231a73df7e205e266fb1198e222814">More...</a><br /></td></tr>
<tr class="separator:ga1e231a73df7e205e266fb1198e222814"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bbfe46af730f1e35b02a1808ff03801"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga8bbfe46af730f1e35b02a1808ff03801">XWT_STR_OFFSET</a>&#160;&#160;&#160;0x28U</td></tr>
<tr class="memdesc:ga8bbfe46af730f1e35b02a1808ff03801"><td class="mdescLeft">&#160;</td><td class="mdescRight">Second Sequence Timer Register Offset.  <a href="group__wdttb__v4__0.html#ga8bbfe46af730f1e35b02a1808ff03801">More...</a><br /></td></tr>
<tr class="separator:ga8bbfe46af730f1e35b02a1808ff03801"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control/Status Register 0 bits</div></td></tr>
<tr class="memitem:gab723ef9be858b9aeb33600ca2d100bd0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gab723ef9be858b9aeb33600ca2d100bd0">XWT_CSR0_WRS_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gab723ef9be858b9aeb33600ca2d100bd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset status Mask.  <a href="group__wdttb__v4__0.html#gab723ef9be858b9aeb33600ca2d100bd0">More...</a><br /></td></tr>
<tr class="separator:gab723ef9be858b9aeb33600ca2d100bd0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga238a7c2e868d73205959bfa8cd8fcf67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga238a7c2e868d73205959bfa8cd8fcf67">XWT_CSR0_WDS_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga238a7c2e868d73205959bfa8cd8fcf67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timer state Mask.  <a href="group__wdttb__v4__0.html#ga238a7c2e868d73205959bfa8cd8fcf67">More...</a><br /></td></tr>
<tr class="separator:ga238a7c2e868d73205959bfa8cd8fcf67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66af9e27001823cc8bc9709fc196d839"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga66af9e27001823cc8bc9709fc196d839">XWT_CSR0_EWDT1_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga66af9e27001823cc8bc9709fc196d839"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable bit 1 Mask.  <a href="group__wdttb__v4__0.html#ga66af9e27001823cc8bc9709fc196d839">More...</a><br /></td></tr>
<tr class="separator:ga66af9e27001823cc8bc9709fc196d839"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control/Status Register 0/1 bits</div></td></tr>
<tr class="memitem:ga8a4f0f57f0cf74799a9d17932ebbfca2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga8a4f0f57f0cf74799a9d17932ebbfca2">XWT_CSRX_EWDT2_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga8a4f0f57f0cf74799a9d17932ebbfca2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable bit 2 Mask.  <a href="group__wdttb__v4__0.html#ga8a4f0f57f0cf74799a9d17932ebbfca2">More...</a><br /></td></tr>
<tr class="separator:ga8a4f0f57f0cf74799a9d17932ebbfca2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Master Write Control bits</div></td></tr>
<tr class="memitem:gaef1c886b782e9f86b9260ca8ecc7fc8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gaef1c886b782e9f86b9260ca8ecc7fc8b">XWT_MWR_AEN_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gaef1c886b782e9f86b9260ca8ecc7fc8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Always Enable Mask.  <a href="group__wdttb__v4__0.html#gaef1c886b782e9f86b9260ca8ecc7fc8b">More...</a><br /></td></tr>
<tr class="separator:gaef1c886b782e9f86b9260ca8ecc7fc8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d5d0ec047ce9d9630edc0fe383f3567"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga9d5d0ec047ce9d9630edc0fe383f3567">XWT_MWR_MWC_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga9d5d0ec047ce9d9630edc0fe383f3567"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Write Control Mask.  <a href="group__wdttb__v4__0.html#ga9d5d0ec047ce9d9630edc0fe383f3567">More...</a><br /></td></tr>
<tr class="separator:ga9d5d0ec047ce9d9630edc0fe383f3567"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Enable &amp; Status Register bits</div></td></tr>
<tr class="memitem:ga643e3b4375dcd8da05f2af9804cdd7b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga643e3b4375dcd8da05f2af9804cdd7b5">XWT_ESR_LBE_MASK</a>&#160;&#160;&#160;0x07000000U</td></tr>
<tr class="memdesc:ga643e3b4375dcd8da05f2af9804cdd7b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last Bad Event Mask.  <a href="group__wdttb__v4__0.html#ga643e3b4375dcd8da05f2af9804cdd7b5">More...</a><br /></td></tr>
<tr class="separator:ga643e3b4375dcd8da05f2af9804cdd7b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf03a853604f976498bf8fd88d55340e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gaf03a853604f976498bf8fd88d55340e2">XWT_ESR_FCV_MASK</a>&#160;&#160;&#160;0x00700000U</td></tr>
<tr class="memdesc:gaf03a853604f976498bf8fd88d55340e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fail Counter Value Mask.  <a href="group__wdttb__v4__0.html#gaf03a853604f976498bf8fd88d55340e2">More...</a><br /></td></tr>
<tr class="separator:gaf03a853604f976498bf8fd88d55340e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaacd2bd7fa6acec9fc6e03dcfb354f850"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gaacd2bd7fa6acec9fc6e03dcfb354f850">XWT_ESR_WRP_MASK</a>&#160;&#160;&#160;0x00020000U</td></tr>
<tr class="memdesc:gaacd2bd7fa6acec9fc6e03dcfb354f850"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Reset Pending Mask.  <a href="group__wdttb__v4__0.html#gaacd2bd7fa6acec9fc6e03dcfb354f850">More...</a><br /></td></tr>
<tr class="separator:gaacd2bd7fa6acec9fc6e03dcfb354f850"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga632b6322025f3f025cb005c453a9b433"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga632b6322025f3f025cb005c453a9b433">XWT_ESR_WINT_MASK</a>&#160;&#160;&#160;0x00010000U</td></tr>
<tr class="memdesc:ga632b6322025f3f025cb005c453a9b433"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Interrupt Mask.  <a href="group__wdttb__v4__0.html#ga632b6322025f3f025cb005c453a9b433">More...</a><br /></td></tr>
<tr class="separator:ga632b6322025f3f025cb005c453a9b433"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e82a9017983f42115d42348e70ed949"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga0e82a9017983f42115d42348e70ed949">XWT_ESR_WSW_MASK</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga0e82a9017983f42115d42348e70ed949"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Second Window Mask.  <a href="group__wdttb__v4__0.html#ga0e82a9017983f42115d42348e70ed949">More...</a><br /></td></tr>
<tr class="separator:ga0e82a9017983f42115d42348e70ed949"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a3959d4536031b508c37288a0f880e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga4a3959d4536031b508c37288a0f880e0">XWT_ESR_WCFG_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga4a3959d4536031b508c37288a0f880e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wrong Configuration Mask.  <a href="group__wdttb__v4__0.html#ga4a3959d4536031b508c37288a0f880e0">More...</a><br /></td></tr>
<tr class="separator:ga4a3959d4536031b508c37288a0f880e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c0d083f02afec23e2fd1000a45ef838"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga5c0d083f02afec23e2fd1000a45ef838">XWT_ESR_WEN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga5c0d083f02afec23e2fd1000a45ef838"><td class="mdescLeft">&#160;</td><td class="mdescRight">Window WDT Enable Mask.  <a href="group__wdttb__v4__0.html#ga5c0d083f02afec23e2fd1000a45ef838">More...</a><br /></td></tr>
<tr class="separator:ga5c0d083f02afec23e2fd1000a45ef838"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9966f0ebfaa911913e1957796156a0ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga9966f0ebfaa911913e1957796156a0ab">XWT_ESR_LBE_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:ga9966f0ebfaa911913e1957796156a0ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last Bad Event Shift.  <a href="group__wdttb__v4__0.html#ga9966f0ebfaa911913e1957796156a0ab">More...</a><br /></td></tr>
<tr class="separator:ga9966f0ebfaa911913e1957796156a0ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga591f46079ca90e4cfb7a6788e60d6982"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga591f46079ca90e4cfb7a6788e60d6982">XWT_ESR_FCV_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:ga591f46079ca90e4cfb7a6788e60d6982"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fail Counter Value Shift.  <a href="group__wdttb__v4__0.html#ga591f46079ca90e4cfb7a6788e60d6982">More...</a><br /></td></tr>
<tr class="separator:ga591f46079ca90e4cfb7a6788e60d6982"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab21f91afca15eb4ce4b710ee2a28fd6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gab21f91afca15eb4ce4b710ee2a28fd6f">XWT_ESR_WRP_SHIFT</a>&#160;&#160;&#160;17</td></tr>
<tr class="memdesc:gab21f91afca15eb4ce4b710ee2a28fd6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Reset Pending Shift.  <a href="group__wdttb__v4__0.html#gab21f91afca15eb4ce4b710ee2a28fd6f">More...</a><br /></td></tr>
<tr class="separator:gab21f91afca15eb4ce4b710ee2a28fd6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9babf40c6d8e8b9062bdf898c543ddf5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga9babf40c6d8e8b9062bdf898c543ddf5">XWT_ESR_WINT_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga9babf40c6d8e8b9062bdf898c543ddf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Interrupt Shift.  <a href="group__wdttb__v4__0.html#ga9babf40c6d8e8b9062bdf898c543ddf5">More...</a><br /></td></tr>
<tr class="separator:ga9babf40c6d8e8b9062bdf898c543ddf5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f717392265a0e113860a0ef6d47d72c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga3f717392265a0e113860a0ef6d47d72c">XWT_ESR_WSW_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga3f717392265a0e113860a0ef6d47d72c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Second Window Shift.  <a href="group__wdttb__v4__0.html#ga3f717392265a0e113860a0ef6d47d72c">More...</a><br /></td></tr>
<tr class="separator:ga3f717392265a0e113860a0ef6d47d72c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1842586eda21a6a9a9ec1f1fd501ce48"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga1842586eda21a6a9a9ec1f1fd501ce48">XWT_ESR_WCFG_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga1842586eda21a6a9a9ec1f1fd501ce48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wrong Configuration Shift.  <a href="group__wdttb__v4__0.html#ga1842586eda21a6a9a9ec1f1fd501ce48">More...</a><br /></td></tr>
<tr class="separator:ga1842586eda21a6a9a9ec1f1fd501ce48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Function Control Register bits</div></td></tr>
<tr class="memitem:ga117ee4c2493a90474a3ca49507d3d7a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga117ee4c2493a90474a3ca49507d3d7a8">XWT_FCR_SBC_MASK</a>&#160;&#160;&#160;0x0000FF00U</td></tr>
<tr class="memdesc:ga117ee4c2493a90474a3ca49507d3d7a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Selected Byte Count Mask.  <a href="group__wdttb__v4__0.html#ga117ee4c2493a90474a3ca49507d3d7a8">More...</a><br /></td></tr>
<tr class="separator:ga117ee4c2493a90474a3ca49507d3d7a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e4ffcc734e76cae5325f089dd008aca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga5e4ffcc734e76cae5325f089dd008aca">XWT_FCR_BSS_MASK</a>&#160;&#160;&#160;0x000000C0U</td></tr>
<tr class="memdesc:ga5e4ffcc734e76cae5325f089dd008aca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte Segment Selection Mask.  <a href="group__wdttb__v4__0.html#ga5e4ffcc734e76cae5325f089dd008aca">More...</a><br /></td></tr>
<tr class="separator:ga5e4ffcc734e76cae5325f089dd008aca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b5d1cdcea538125ec8147a393f4698a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga8b5d1cdcea538125ec8147a393f4698a">XWT_FCR_SSTE_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga8b5d1cdcea538125ec8147a393f4698a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Second Sequence Timer Enable Mask.  <a href="group__wdttb__v4__0.html#ga8b5d1cdcea538125ec8147a393f4698a">More...</a><br /></td></tr>
<tr class="separator:ga8b5d1cdcea538125ec8147a393f4698a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga692cb7a25cf383b1440a7294dee8e01f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga692cb7a25cf383b1440a7294dee8e01f">XWT_FCR_PSME_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga692cb7a25cf383b1440a7294dee8e01f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Program Sequence Monitor Enable Mask.  <a href="group__wdttb__v4__0.html#ga692cb7a25cf383b1440a7294dee8e01f">More...</a><br /></td></tr>
<tr class="separator:ga692cb7a25cf383b1440a7294dee8e01f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4ac9d924cdd9b2e60598cc352fa5c4f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga4ac9d924cdd9b2e60598cc352fa5c4f2">XWT_FCR_FCE_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga4ac9d924cdd9b2e60598cc352fa5c4f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fail Counter Enable Mask.  <a href="group__wdttb__v4__0.html#ga4ac9d924cdd9b2e60598cc352fa5c4f2">More...</a><br /></td></tr>
<tr class="separator:ga4ac9d924cdd9b2e60598cc352fa5c4f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22090b12465623ea42b83cd715cfeea5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga22090b12465623ea42b83cd715cfeea5">XWT_FCR_WM_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga22090b12465623ea42b83cd715cfeea5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Window WDT Mode Mask.  <a href="group__wdttb__v4__0.html#ga22090b12465623ea42b83cd715cfeea5">More...</a><br /></td></tr>
<tr class="separator:ga22090b12465623ea42b83cd715cfeea5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2603ea5819ae2a751e27bcf9c0656320"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga2603ea5819ae2a751e27bcf9c0656320">XWT_FCR_WDP_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga2603ea5819ae2a751e27bcf9c0656320"><td class="mdescLeft">&#160;</td><td class="mdescRight">Window WDT Disable Protection Mask.  <a href="group__wdttb__v4__0.html#ga2603ea5819ae2a751e27bcf9c0656320">More...</a><br /></td></tr>
<tr class="separator:ga2603ea5819ae2a751e27bcf9c0656320"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab3779c880caf61127155195ea6a5b181"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gab3779c880caf61127155195ea6a5b181">XWT_FCR_SBC_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gab3779c880caf61127155195ea6a5b181"><td class="mdescLeft">&#160;</td><td class="mdescRight">Selected Byte Count Shift.  <a href="group__wdttb__v4__0.html#gab3779c880caf61127155195ea6a5b181">More...</a><br /></td></tr>
<tr class="separator:gab3779c880caf61127155195ea6a5b181"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33eee5e5fe8e1e8f1f9e1ff6a680f308"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga33eee5e5fe8e1e8f1f9e1ff6a680f308">XWT_FCR_BSS_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga33eee5e5fe8e1e8f1f9e1ff6a680f308"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte Segment Selection Shift.  <a href="group__wdttb__v4__0.html#ga33eee5e5fe8e1e8f1f9e1ff6a680f308">More...</a><br /></td></tr>
<tr class="separator:ga33eee5e5fe8e1e8f1f9e1ff6a680f308"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28564e4563b39127f547e095f9cd40c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga28564e4563b39127f547e095f9cd40c8">XWT_FCR_SSTE_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga28564e4563b39127f547e095f9cd40c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Second Sequence Timer Enable Shift.  <a href="group__wdttb__v4__0.html#ga28564e4563b39127f547e095f9cd40c8">More...</a><br /></td></tr>
<tr class="separator:ga28564e4563b39127f547e095f9cd40c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9d1b7fbe234fd6e358d922f596386c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gac9d1b7fbe234fd6e358d922f596386c5">XWT_FCR_WM_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gac9d1b7fbe234fd6e358d922f596386c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Window WDT Mode Shift.  <a href="group__wdttb__v4__0.html#gac9d1b7fbe234fd6e358d922f596386c5">More...</a><br /></td></tr>
<tr class="separator:gac9d1b7fbe234fd6e358d922f596386c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:gadf392cff302c8ea88ba33c545e757d4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gadf392cff302c8ea88ba33c545e757d4b">XWdtTb_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:gadf392cff302c8ea88ba33c545e757d4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="group__wdttb__v4__0.html#gadf392cff302c8ea88ba33c545e757d4b">More...</a><br /></td></tr>
<tr class="separator:gadf392cff302c8ea88ba33c545e757d4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64a7b4a2766f990ebafeed1978593308"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga64a7b4a2766f990ebafeed1978593308">XWdtTb_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:ga64a7b4a2766f990ebafeed1978593308"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="group__wdttb__v4__0.html#ga64a7b4a2766f990ebafeed1978593308">More...</a><br /></td></tr>
<tr class="separator:ga64a7b4a2766f990ebafeed1978593308"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa6b4b0d4c816cd9bd6da3c9fe7caac3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#gafa6b4b0d4c816cd9bd6da3c9fe7caac3">XWdtTb_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__wdttb__v4__0.html#gadf392cff302c8ea88ba33c545e757d4b">XWdtTb_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
<tr class="memdesc:gafa6b4b0d4c816cd9bd6da3c9fe7caac3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read from the specified WdtTb core's register.  <a href="group__wdttb__v4__0.html#gafa6b4b0d4c816cd9bd6da3c9fe7caac3">More...</a><br /></td></tr>
<tr class="separator:gafa6b4b0d4c816cd9bd6da3c9fe7caac3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga36d539f7262d0267924d2ef5612f0cc2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__wdttb__v4__0.html#ga36d539f7262d0267924d2ef5612f0cc2">XWdtTb_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;<a class="el" href="group__wdttb__v4__0.html#ga64a7b4a2766f990ebafeed1978593308">XWdtTb_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:ga36d539f7262d0267924d2ef5612f0cc2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to the specified WdtTb core's register.  <a href="group__wdttb__v4__0.html#ga36d539f7262d0267924d2ef5612f0cc2">More...</a><br /></td></tr>
<tr class="separator:ga36d539f7262d0267924d2ef5612f0cc2"><td class="memSeparator" colspan="2">&#160;</td></tr>
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